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1 ? fn3125.7 hi-301, hi-303 cmos analog switches the hi-301 and hi-303 series of switches are monolithic devices fabricated using cmos technology and the intersil dielectric isolation process. these switches feature break before-make switching, low and nearly constant on resistance over the full analog signal range, and low power dissipation, (a few mw for the hl-301 and hi-303). the hi-301 and hi-303 are ttl compatible and have a logic ?0? condition with an input less than 0.8v and a logic ?1? condition with an input greater than 4v. (see pinouts for switch conditions with a logic ?1? input.) features analog signal range ( 15v supplies) . . . . . . . . . . 15v low leakage at 25 o c . . . . . . . . . . . . . . . . . . . . . . . 40pa low leakage at 125 o c . . . . . . . . . . . . . . . . . . . . . . . 1na low on resistance at 25 o c . . . . . . . . . . . . . . . . . . . 35 ? break-before-make delay . . . . . . . . . . . . . . . . . . . . 60ns charge injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pc ttl, cmos compatible symmetrical switch elements low operating power (typ) . . . . . . . . . . . . . . . . . . . . 1.0mw applications sample and hold (i.e., low leakage switching) op amp gain switching (i.e., low on resistance) portable, battery operated circuits low level switching circuits dual or single supply systems functional diagram pinouts switch states shown for a logic ?1? input spst hi-301 (soic) top view dual spdt hi-303 (pdip, cerdip, soic) top view ordering information part number temp. range ( o c) package pkg. no. hi9p0301-5 0 to 75 14 ld soic m14.15 hi1-0303-2 -55 to 125 14 ld cerdip f14.3 hi1-0303-5 0 to 75 14 ld cerdip f14.3 hi3-0303-5 0 to 75 14 ld pdip e14.3 hi9p0303-5 0 to 75 14 ld soic m14.15 hi9p0303-9 -40 to 85 14 ld soic m14.15 s n in p d logic sw1 sw2 0offon 1onoff nc d 1 nc s 1 nc in gnd v+ d 2 nc s 2 nc nc v- 1 2 3 4 5 6 7 14 13 12 11 10 9 8 logic sw1, sw2 sw3, sw4 0offon 1onoff 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc s 3 d 3 d 1 s 1 in 1 gnd v+ s 4 d 4 d 2 s 2 in 2 v- data sheet may 2002 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 schematic diagrams switch cell digital input buffer and level shifter mn2b in mn3b a mp4b mp3b mp2b mn4b mp5b v+ mn6b v- out mp1b a mn1b mp3a mn3a mp4a mn4a mp2a mn2a mp1a mn1a d2a 200 ? v+ logic gnd v- in mp5a mn5a mp6a mn6a mp7a mn7a mp8a mn8a a a switch cell driver (one per switch cell) d1a hi-301, hi-303
3 absolute maximum ratings thermal information voltage between supplies (v+ to v-) . . . . . . . . . . . . . . . 44v ( 22v) digital input voltage. . . . . . . . . . . . . . . . . . . . . . (v+) +4v to (v-) -4v analog input voltage . . . . . . . . . . . . . . . . . . (v+) +1.5v to (v-) -1.5v typical derating factor . . . . . . . . . 1.5ma/mhz increase in iccop esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions temperature range hi-30x-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c hi-30x-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c hi-30x-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 80 24 pdip package . . . . . . . . . . . . . . . . . . . 90 n/a soic package . . . . . . . . . . . . . . . . . . . 120 n/a maximum junction temperature ceramic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications supplies = +15v, -15v; v in = logic input. v in - for logic ?1? = 4v, for logic ?0? = 0.8v. unless otherwise specified parameter temp ( o c) -2 -5, -9 units min typ max min typ max dynamic characteristics switch on time, t on 25 - 210 300 - 210 300 ns switch off time, t off 25 - 160 250 - 160 250 ns break-before-make delay, t open 25 -60- -60-ns charge injection voltage, ? v (note 7) 25 - 3 - - 3 - mv off isolation (note 6) 25 - 60 - - 60 - db input switch capacitance, c s(off) 25 -16- -16-pf output switch capacitance, c d(off) 25 -14- -14-pf output switch capacitance, c d(on) 25 -35- -35-pf digital input capacitance, c in 25 - 5 - - 5 - pf digital input characteristics input low level, v inl full - - 0.8 - - 0.8 v input high level, v inh (note 10) full 4 - - 4 - - v input leakage current (low), i inl (note 5) full - - 1 - - 1 a input leakage current (high), i inh (note 5) full - - 1 - - 1 a analog switch characteristics analog signal range full -15 - +15 -15 - +15 v on resistance, r on (note 2) 25 - 35 50 - 35 50 ? full - 40 75 - 40 75 ? off input leakage current, i s(off) (note 3) 25 - 0.04 1 - 0.04 5 na full - 1 100 - 0.2 100 na off output leakage current, i d(off) (note 3) 25 - 0.04 1 - 0.04 5 na full - 1 100 - 0.2 100 na on leakage current, i d(on) (note 4) 25 - 0.03 1 - 0.03 5 na full - 0.5 100 - 0.2 100 na hi-301, hi-303
4 power supply characteristics current, i+ (note 8) 25 - 0.09 0.5 - 0.09 0.5 ma full - - 1 - - 1 ma current, i- (note 8) 25 - 0.01 10 - 0.01 100 a full - - 100 - - - a current, i+ (note 9) 25 - 0.01 10 - 0.01 100 a full - - 100 - - - a current, i- (note 9) 25 - 0.01 10 - 0.01 100 a full - - 100 - - - a notes: 2. v s = 10v, i out = 10ma. on resistance derived from the voltage measured across the switch under these conditions. 3. v s = 14v, v d = 14v. 4. v s = v d = 14v. 5. the digital inputs are diode protected mos gates and typical leakages of 1na or less can be expected. 6. v s = 1v rms , f = 500khz, c l = 15pf, r l = 1k. 7. v s = 0v, c l = 10nf, logic drive = 5v pulse. switches are symmetrical; s and d may be interchanged. charge injection = q = c l x ? v. 8. v in = 4v (one input, all other inputs = 0v). 9. v in = 0.8v (all inputs). 10. to drive from dtl/ttl circuits, pullup resistors to +5v supply are recommended. electrical specifications supplies = +15v, -15v; v in = logic input. v in - for logic ?1? = 4v, for logic ?0? = 0.8v. unless otherwise specified (continued) parameter temp ( o c) -2 -5, -9 units min typ max min typ max test circuits and waveforms figure 1a. test circuit figure 1b. measurement points figure 1. switch t on and t off switch type v inh hi-301, hi-303 4v 15v v+ d r l 300 ? c l 33pf v- -15v gnd logic v s = +3v s input v o switch output logic ?1? = switch on logic input 0v v s 0v switch output v inh 50% 50% 10% 90% t on t off hi-301, hi-303
5 figure 2a. test circuit figure 2b. ttl logic input figure 2c. v analog = 10v figure 2d. v analog = 5v figure 2e. v analog = 0v figure 2f. v analog = -5v test circuits and waveforms (continued) +15v v+ d r l 10k ? c l 10pf v- -15v gnd v logic v gen r gen = 0 s in time ( s) 6 4 2 0 0 0.4 0.8 1.2 1.6 l o g i c i n p u t ( v ) logic input time ( s) 10 5 0 00.40.81.21.6 o u t p u t v o l t a g e ( v ) v gen = 10v (note 11) time ( s) 5 0 0 0.4 0.8 1.2 1.6 o u t p u t v o l t a g e ( v ) v gen = 5v time ( s) 5 0 0 0.4 0.8 1.2 1.6 o u t p u t v o l t a g e ( v ) v gen = 0v -5 time ( s) 0 0 0.4 0.8 1.2 1.6 o u t p u t v o l t a g e ( v ) v gen = -5v -5 hi-301, hi-303
6 figure 2g. v analog = -10v note: 11. if r gen , r l or c l is increased, there will be proportional increases in rise and/or fall rc times. figure 2. switching waveforms for various analog input voltages figure 3a. test circuit figure 3b. measurement points figure 3. break-before-make delay (t open ) test circuits and waveforms (continued) time ( s) 0 0 0.4 0.8 1.2 1.6 o u t p u t v o l t a g e ( v ) v gen = -10v -5 -10 switch type v inh hi-301, hi-303 5v v+ d 2 r l2 c l2 v- -15v gnd logic v s2 = +3v s 2 input out 1 out 2 d 1 s 1 v s1 = +3v r l1 c l1 15v logic ?1? = switch on logic input 0v 0v switch outputs v inh 50% 50% t open 50% 50% 0v out 1 out 2 r l1 = r l2 = 300 ? c l1 = c l2 = 33pf t open hi-301, hi-303
7 typical performance curves figure 4. r ds(on) vs v d figure 5. r ds(on) vs v d figure 6. device power dissipation vs switching frequency (single logic input) figure 7. off isolation vs frequency figure 8. i s(off) or i d(off) vs temperature ? figure 9. i d(on) vs temperature ? ? the net leakage into the source or drain is the n-channel leakage minus the p-channel leakage. this difference can be positive , negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. drain voltage (v) d r a i n t o s o u r c e o n r e s i s t a n c e ( ? ) 80 60 40 20 0 -15 -10 -5 0 5 10 15 v+ = +15v, v- = -15v 125 o c 25 o c -55 o c drain voltage (v) d r a i n t o s o u r c e o n r e s i s t a n c e ( ? ) 80 60 40 20 0 -15 -10 -5 0 5 10 15 t a = 25 o c a v+ = +15v, v- = -15v b v+ = +10v, v- = -10v c v+ = +7.5v, v- = -7.5v d v+ = +5v, v- = -5v a b c d v+ = +15v, v- = -15v t a = 25 o c, v s = 15v, r l = 2k 110 logic switching frequency (50% duty cycle) (hz) 100 1k 10k 100k 1m 0.1 1.0 10 100 p o w e r d i s s i p a t i o n ( m w ) r l = 100 ? v+ = +15v, v- = -15v c load = 30pf, v s = 1v rms 10 5 r l = 1k ? frequency (hz) 10 6 10 7 10 8 100 80 60 40 20 0 o f f i s o l a t i o n ( d b ) temperature ( o c) v+ = +15v, v- = -15v 10.0 1.0 0.1 0.01 25 75 125 s o u r c e o r d r a i n o f f l e a k a g e c u r r e n t ( n a ) temperature ( o c) v+ = +15v, v- = -15v 10.0 1.0 0.1 0.01 25 75 125 i d ( o n ) ( n a ) | v d | = | v s | = 14v hi-301, hi-303
8 figure 10. output on capacitance vs drain voltage figure 11. digital input capacitance vs input voltage figure 12. switching time vs temperature figure 13. switching time vs negative supply voltage figure 14. switching time and break-before-make time vs positive supply voltage figure 15. input switching threshold vs positive supply voltage typical performance curves (continued) drain voltage (v) 10 12 14 16 8 6 4 2 0 60 50 40 30 20 o u t p u t o n c a p a c i t a n c e ( p f ) input voltage (v) 10 12 14 16 8 6 4 2 0 16 12 8 4 i n p u t c a p a c i t a n c e ( p f ) transition (indeterminate due to active input) temperature ( o c) 65 85 105 125 45 25 5 -35 -55 300 200 100 s w i t c h i n g t i m e ( n s ) -15 t on t off v+ = +15v, v- = -15v v inh = 4.0v, v inl = 0v negative supply (v) 10 15 5 0 300 200 100 s w i t c h i n g t i m e ( n s ) v+ = +15v, t a = 25 o c v inh = 4v, v inl = 0v t on t off positive supply voltage (v) 10 15 5 0 1.8 0.6 s w i t c h i n g t i m e / b r e a k - b e f o r e - m a k e t i m e ( s ) v- = -15v, t a = 25 o c v inh = 4.0v, v inl = 0v t on t off 1.6 1.4 1.2 1.0 0.8 0.4 0.2 0 t open only positive supply voltage (v) 10 15 5 0 7 1 i n p u t s w i t c h i n g t h r e s h o l d ( v ) 6 5 4 3 2 0 v- = -15v, t a = 25 o c hi-301, hi-303
9 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e14.3 (jedec ms-001-aa issue d) 14 lead dual-in-line plastic package symbol inches millimeters notes minmaxminmax a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n14 149 rev. 0 12/93 hi-301, hi-303
10 hi-301, hi-303 ceramic dual-in-line frit seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f14.3 mil-std-1835 gdip1-t14 (d-1, configuration a) 14 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa -0.015-0.38 - bbb -0.030-0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n14 148 rev. 0 4/94
11 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certification. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circui t design and/or specifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furn ished by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com hi-301, hi-303 small outline plastic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes minmaxminmax a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93

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